1. Field of the Invention
The present invention relates in general to a testing method, more specifically, to a method of testing for static random access memory (SRAM) pull-down transistor sub-threshold leakage to pick out the defective SRAM products.
2. Description of the Related Art
SRAM is a commonly used memory device, and is volatile, that is when the power source supplied to SRAM is shut down, the data stored in SRAM disappear. The memory cells in SRAM are used for storing data by changing the conduction state of the internal transistors in a memory cell. This is quite different from dynamic RAM (DRAM) which stores data by charging and discharging capacitors. The access speed of SRAM is very fast so it is widely applied to computer systems as cache memory.
FIG. 1A illustrates a circuit block diagram of a SRAM cell. In the figure, a latch circuit consists of transistors M1, M2, M3, and M4, wherein transistors M3 and M4 serve as active loads or pull-up devices (M3 and M4 can be replaced with resistors). The complement logic signal pairs are generated at terminals X and Y, that is, the data written to memory cells are stored in the drain terminals of pull-down transistors M1 and M2. Word line W is used for addressing and controlling the on/off states of the controlling transistors M5 and M6. The data are written in or read from the terminals X and Y through the bit lines B and B.
In FIG. 1A, the sources of the pull-down transistors M1 and M2 are connected to ground. However, because the path from source to ground is connected by a conductive line (such as polysilicon, metal, n+diffusion region) and the source of the pull-down transistor is made of a n+polysilicon region, there is parasitic resistance formed between the sources and ground. Consequently, the relationship between the sources of the pull-down transistors M1 and M2 can be depicted as FIG. 1B. In FIG. 1B, the source of the transistor M2 is grounded, and the source of the transistor M1 connected to the ground through an equivalent parasitic resistor Rn. The parasitic resistor Rn degrades the SRAM performance.
FIG. 2 illustrates a circuit diagram of two memory cells 1 and 2 at the adjoining word lines WL.sub.X and WL.sub.X+1 respectively. The sources of the pull-down transistors 10 and 20 in cell 1 and 2 are connected together and grounded through a parasitic resistor Rs. The pull-up devices in the two memory cells are resistors (R1.about.R4).
Data "0" and "1" are written into terminals A and B in cell 1 respectively, and data "0" and "1" are written into terminals C and D in cell 2 respectively. In this case, the voltage at terminal A is of low logic "0" and the pull-down transistor 10 is turned on (because the voltage at terminal B is of high logic "1"), thereby generating a current I.sub.1 flowing from the voltage source V.sub.DD through resistor R1, pull-down transistor 10, resistor Rs to ground. Similarly in cell 2, a current I.sub.2 is generated and flows from the voltage source V.sub.DD through resistor R3, pull-down transistor 20, resistor Rs to ground.
When the word line WL.sub.X is activated or turned on, the transistors 14 and 16 in cell 1 are also turned on, and a current I.sub.p is generated and flows through pull-down transistor 10 and parasitic resistor Rs to ground. If the parasitic resistor has high resistance, the voltage at terminal Q is raised and high voltage is coupled to terminals A and C. Thus, the voltages to bias the gates of the transistors 12 and 22 are increased, and the sub-threshold leakage of the pull-down transistors 12 and 22 is increased, and the data stored in memory cells may be changed.
Furthermore, in the fabrication process of SRAM, the threshold voltage of the pull-down transistors 12 and 22 may be lower than the normal value due to ion implantation defects and channel effect, etc. Therefore, because the voltages to bias the gates of the transistors 12 and 22 are raised, transistors 12 and 22 may be turned on. Finally, for a long time period, the data "0" and "1" stored in A and B terminals will be changed to "1" and "0". Similarly, the data "0" and "1" stored in C and D terminals will be changed to "1" and "0".
The above mentioned problems is difficult to be detected in previous by general test methods. The effects due to the leakage of transistors 12 and 22 may occur, only when the word line have been turned on for a long time period. However, the operation of the SRAM is normal in the general state. Therefore, if the above mentioned problems occur, this causes the user serious trouble, and is difficult for the manufacturer to debug.